Closed loop controller having digital integrator with variable gain



May 19, 1970 J. o. JACQUES ET AL 3,513,302

CLOSED LOP CONTROLLER HAVING DIGITAL l INTEGRATOR WITH VARIABLE GAIN 13 Sheets-Sheet 1 Filed Jan. 17, 1966 J. O. JACQUES ET AL CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN May 19, 1970 Filed Jan. 17, 196e Z m @ff n W w m l l l I I l I I l l l I l I l l l l l I 11.4 L H l I W 2J M M M, m L f of, i VINI; w .L1

May 19, 1970 Filed Jan. 17. 1966 CLOSED LoP o. JACQUES x-:TAL

CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN l5 Sheets-Sheet 5 May 19, 1970 J. o. JACQUES ETAL 3,513,302

CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN Filed Jan. 17, 1966 13 Sheets-Sheet 4 May 19, 1970 CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN Filed Jan. 17. 196e A /0 /fl/P/TE /J/w J. O. JACQUES ET AL 13 Sheens-Sheerl 5 5f fraz www@ @M5 m @f/023 m4n/Ma 5a.

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May 19, 1970 Filed Jari. 17, 1966 J. o. JACQUES ET AL 3,513,302

CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN v 13 SheetsSheet 7 May 19, 1970 J, Q, JACQUES ET AL 3,513,302

OLOsED LOOP CONTROLLER HAVING DIGITAL INTEGRATOE WITH VARIABLE GAIN May 19, 1970 Filed Jan. 17, 1966 lJ. O. JACQUES ET AL CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN 13 Sheets-Sheet 9 r I y Falec May 19, 1970 J. o. JACQUES ET AL. 3,513,302

CLOSED LOOP CONTROLLER HAVING DIGITAL Filed Jan. 17, 1966 INTEGRATOR WITH VARIABLE GAIN 13 Sheets-Sheet lO FIG.3D

May 19, 1970 Filed Jan. 1'7, 1966 J. O. JACQUES ET AL CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN 13 SheetsSheet 11 May 19, 1970 J. O. JACQUES ETAL. 3,513,302

CLOSED LOOP CONTROLLER HAVING DIGITAL l INTEGRATOR WITH VARIABLE GAIN Filed Jan. 17. 196e 15 sheets-sheet 12 FIG.3F

May 19, 1970 1 JACQUES ET AL 3,513,302

CLOSED LOOP CONTROLLER HAVING DIGITAL INTEGRATOR WITH VARIABLE GAIN United States Patent O" U.S. Cl. 23S- 151.1 17 Claims ABSTRACT OF THE DISCLOSURE A two term process control system that generates an output control signal from successive digital error signals by dividing the error signals in accordance with a selected integral gain term, and adding the divided quantities to provide an integral value, while also providing a proportional value with a different `gain term, and combining the two values to provide the output control signal.

This invention relates generally to closed loop controllers and particularly to the means for performing integration in such devices.

Feedback control systems commonly compare an output or process variable signal from the controlled device with a value representing the desired output or set point signal. The result of the comparison between the process variable signal and the set point is a deviation or control error signal, The error signal is modified by means such as ampliiers and integrators to derive a control signal which represents the new position for a valve or other controlled device.

In a two mode control system, modification of the error signal follows the general form:

P=KPE|KIf0Edt where P is the output ofthe control system,

KP is the proportional gain constant;

0E is the deviation or error signal;

KI is the integral gain constant; and

fEdt is the time integral of the control error signal.

A more complete discussion of this type of two mode control is contained in the Handbook of Automation Computation and Control, John Wiley & Sons, vol. 3 at p. 7-05.

While analog t-wo mode controllers have been built to implement this control equation, there are practical limitations which have prevented the full achievement of this function. This primary difliculty has been in the mechanization of the integral term. Electrical integrators ofthe resistance-capacitance type have been used to achieve reset or integration time constants of minutes. This time is limited by the maximum practical size and cost of storage capacitors and the maximum upper limit of a stable impedance in parallel with the storage capacitor.

It can be seen that the shorter the integration time constant, the higher the integration gain must |be to provide a change in the controller output for a given error signal. For example, a l unit error signal 0E is fed to an integrator having a 30 minute time constant to provide the minimum change in the controller output signal. If this controller has an integration gain constant of KI, it can 'be seen that the gain constant can :be KI/ 2 if the time constant is lengthened to 60 minutes.

The use of a digital storage device for the integral term provides an unlimited time constant. While digital storage devices have been used in follow-up control systems such 3,513,302 Patented May 19, 1970 ICC as used in machine tool controllers, they have not been ygenerally employed in two mode controllers. Furthermore7 gain adjustment of the digital hardware tends to be complex unless limited to the inilexible adjustment in powers of two. Systems heretofore available for such purposes, however, have been excessively complex and expensive.

It is, therefore, an object of this invention to provide an improved controller.

It is another object of this invention to provide a closed loop controller having a digital integrator as well as a proportional control component.

It is another object of this invention to provide a digital integrator having a variable gain constant.

Still another object of this invention is to provide a closed loop control system having improved integral action.

In accordance with the invention, the error signal in a multi-channel process control system is modied *both in accordance with an integral term and a proportional term. The integral term is digitally generated, stored, and used in successive scans of a channel.

An analog process variable signal is converted into a time interval. During the time interval, clock pulses are fed to a binary counting register causing it to count up, so as to accumulate a count representing the process variable. At the end of the time interval, the register contains a digital value corresponding to the analog process variable signal. A train of pulses representing the set point value is then fed to the register, causing it to count in the opposite direction. The value remaining after the set point has been counted in is the error or difference between the process variable and the set point. The error signal is then converted into a pulse train and applied to the integration gain channel for the loop. The integration gain channel includes both a variable time switching device, termed a multi-rate sampler, and a variable counter divider. If the necessary number of sampling intervals have occurred, the multi-rate sampler operates to apply the error pulse train to a series of binary triggers which serve to divide the pulse train by successive factors Of two. The length of the trigger divider may be varied to establish a gain constant to accommodate the process loop with Iwhich it is associated, and adjustment of the sampling interval allows a further range for the integration gain constant. The carry pulses from any selected trigger are added to the previous integral, to provide an updated integral term `which is then used in the derivation of an output signal.

As an example of the mode of operation, assume that the sampling interval is one-fifth second and the multi-rate sampler is set to operate on every tenth sample. One sample of error pulses will be fed to the trigger divider every two seconds. Further assuming that there are four trigger dividers and two error pulses, there will then be a one pulse output to the integral value at intervals of 16 seconds The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings:

FIG. l is a generalized block diagram representation of the principal elements of a digital process system incorporating features in accordance with the invention;

FIG. 2 is a schematic and detailed block diagram, comprising sheets designated FIGS. 2A to 2E respectively, of a digital process controller in accordance with the invention, showing details thereof, and

FIG. 3, comprising separate sheets designated FIGS. 3A to 3G is a separate representation of the gating control and gate circuits utilized in the arrangement of FIG. 2.

In the use of FIG. 2, the separate sheets designated A through E respectively, should be aligned from left to right.

In the use of FIG. 3, the separate sheets designated A through G respectively, should be aligned from top to bottom.

The diagram of FIG. l shows in generalized form a digital process control system for concurrently adjusting and maintaining a number of individual operative set points, representing different system variables, within a process system 20. For the present example, it will be assumed that twenty different variables are controlled, and that a corresponding number of controllers 21 are operated by the process control system in response to directly or indirectly related values derived from sensors 22. The control system may be referred to therefore as a multi-function or multiloop controller, and operates continuously in highly integrated fashion. The controllers 21 and sensors 22 may be conventional analog devices and need not be further described in detail. The set points are chosen or adjusted, as described in detail hereafter, in accordance with known considerations determined with respect to the process system 20, and may be affected by external automatic control or by operator control during operation.

Signals derived in the multiple parallel channels from the sensors 22 represent the process variables (hereafter PV) and are applied to an input multiplexer 25 that may be generalized as a first switch S1 operated at a first known rate. Signals from the input multiplexer 25 are applied in the single output channel to an analog to digital converter 26 of the type that effectively converts the amplitude of the applied input signal to a signal defining a variable time duration. This time duration is used in controlling the application of clock pulses to a first summing counter, termed the A register 28. The time interval during which the pulses provided from a standard clock source are applied to the A register 28 determines, of course, the number of pulses applied, so that the PV value is represented in digital form.

The multi-function controller system performs a two term control computation in adjusting in process variable relative to a stored set point. The set point is derived from a recirculating storage 30, typically a delay line system although a drum, disc or other recirculating memory may be used. Read and write circuits 31, 32 respectively provide for access from and entry to the storage 30. For ease of understanding only, the read circuits 31 are shown as separating the set point and integral values in playback, although this separation is accomplished by conventional gating circuits. The set point (also termed SP herein) is entered as a digital count in the B register 35, with the A register 28 receiving the PV value. Subsequently, a series of pulses is applied to drive the A register 28 and the B register 35 to zero, so that one value is effectively subtracted from the other. The result, taking into account certain limit adjustments described below, constitutes the error quantity and is presented by the A register 28 as a digital count.

The error represents the subtraction of one quantity from the other in a sense dependent upon whether forward or reverse control is used and upon the particular limit relationships. Forward or reverse control is used depending upon the sense in which adjustment of a given controller causes a variation of the associated process variable. A pulse series and an equivalent pulse duration representative of the amplitude of the error are provided for further processing by counting down the A register 28 at the clock rate.

A single term control computation would adjust the error by a given proportional, integral, or other factor in deriving a control signal suitable for application to the associated controller. The present system provides a two term control computation in which, for each channel, an analog proportionality term Kp and an integral term KI are each applied to the error signal in deriving the control signal. For this purpose, proportional gain circuits 33 convert the pulse series derived from the A register 28 into a lesser number of pulses in a ratio depending upon the proportionality factor, and apply the adjusted count to a third summing counter or C register 36 which also receives the updated integral term in digital form from the second summing counter or B register 35. The summation of these two terms, provided as the output signal from the C register 36, is the output control or corrective signal for the specific channel. The integral term is updated by combining the summation of the previous integral term derived from the read circuits 31 with the current error level, as adjusted by the integral gain constant in the integral gain circuits 34.

The three summing counter units 28, 35 and 36 are counted down or up, for determinable intervals, under the command of circuits here designated the count and count detect controls 37. The circuits 37, as described in detail below, operate at chosen clock rates to drive the various summing counters simultaneously in the same or different senses until selected states are reached. Thus, if two counters containing different counts are down-counted synchronously, the count remaining in one after the other has reached zero is the difference quantity. Similarly, the count stored in one may be transferred, with or without modification, into another by counting synchronously in opposite senses.

A suitably small fractional integral term may be multiplied against the incoming error signal by utilizing both a variably timed switch 38, operated in synchronism with the input and output multiplexers, and a variable pulse divider circuit 39, here designated K1. Thus, from the integral term for the particular channel derived from the read circuits 31, and from the integral component representative of the current error signal derived from the integral gain circuits 34, the count applied to the C register 36 represents the updated integral which is also replaced in storage.

The digital output signal provided from the C register 36 is applied through a digital to analog converter 40, the output multiplexer 41, and a suitable holding amplifier circuit 43, so that an output control signal of duration sufcient to cause adjustment of the associated controller is provided during the interval in `which the output multiplexer 41 addresses the particular channel.

It will be appreciated that the system thus far broadly described has a number ot advantages as a process controller. It is extremely flexible in operation because of its organization and because of its digital nature. Set points and gain constants may be varied in operation either by the operator or by an external data processing system, it desired, because indirect or direct access may be had to the registers. The manipulation of values in digital form further permits the system to be operated generally in conjunction with a central data processing system when desired. The two term control computation improves both the stability and accuracy of this system over a single term control computation. Major excursions in the error signal are corrected principally by the presence of the proportional term although some contribution is also derived from the integral term. Drift and other long term, small magnitude, errors that would not ordinarily be corrected by the proportional term are corrected by the integral term. The integral term is digitally stored, and therefore may be retained indefinitely without being subject to or introducing error.

This broad description of the system encompasses a substantial number of specific features described in detail hereafter. The drawings comprise a detailed block diagram (FIG. 2) of the system, showing the organization of the various input and output systems as well as control and indicator devices, including multiposition switches, individual control switches, adjustment devices and indicators. The complete system as represented in FIG. 2, comprises separate sheets denoted FIGS. 2A to 2E. While all the principal components are described in detail hereafter, a detailed description of the logical gating circuits would be repetitious for those skilled in the art inasmuch as each of the terms applied in the form of signals to each gate is represented in the figures. It is considered more convenient and clear to present the various modes and gating sequences separately in FIG. 3, comprising sheets FIGS. '3A to 3G, inclusive, to provide the functioning of the logical gating circuits in a more readily visualized format.

In FIG. 3, the various principal modes of system operation are identified as a sequence of rectangles 301-312. The individual gates associated with each mode are disposed in laterally extending fashion to illustrate the manner in which the specific control signals are generated for each control function and change of state is utilized in operation in a particular mode. Along with the successive modes, states or levels of the system, FIG. 3 shows the individual signals provided from a group of latches that are down-counted to identify the modes. Only the latches in the on condition are shown in the block identifying the mode. Although not shown in FIG. 2 for simplicity, the latches control shift from one mode to the next in the following sequence:

CONVERT (3M-FIG. 3A)

READY 1 (302-FIG. 3B)

COMPUTE ERROR (303-FIG. 3B)

ADDRESS DELAY LINE (304-FIG. 3C)

READY 2 (30S-FIG. 3C)

TWO TERM COMPUTE (S-FIG. 3D)

WRITE STORAGE (3M-FIG. 3E)

TRANSFER INTEGRAL TO C REG. (M8-FIG. 3E) ADVANCE CHANNEL-SET DAC (309-FIG. 3F) INTERLOCK (310-FIG. 3G)

LOAD STATE (311-FIG. 3G)

END LOAD (312-FIG. 3G)

It will be noted that the modes are distinguished by a change of state of the latches. At each mode, a number of gates are conditioned to provide outputs used for further gating or advance. These gates are either AND gates, designated by the multiplication symbol or OR gates, designated by the addition symbol (-j-), in conventional fashion. Where gates are repeated for convenience of reference in different parts of FIG. 3, they bear the same numeral designation. When so shown, however, they are conditioned by different mode signals.

Shifts between the mode rectangles 301-312 in FIG. 3 are undertaken upon the passage of gate signals through gates serially connecting the rectangles and corresponding to the latch controls. Certain of the advances are governed by signals from a Bit Ring Circuit (generating signals1 designated BR1 through BR11 respectively) associated with the recirculating memory and described in detail below. The Bit Ring Circuit not only governs the timing of data into and out of the recirculating storage, but provides a time sequence by which other gating functions may be performed.

It should be appreciated that for each channel separate circuits are used for set point adjustment, alarm indications and gain selection.

Referring now to FIG. 2, comprising the separate sheets designated FIGS. 2A to 2E inclusive, reference is made to the separate units that are subject to operator adjustment or control, as well as those units previously broadly referred to in the description of FIG. l. The operator has at his command a display function switch 50 and a channel select switch 52, by which a given channel may be chosen for adjustment of set point, limit or alarm conditions, for testing purposes or for the performance of other functions. Both the display function switch 50 and the channel select switch 52 are shown in FIG. 2D. A separate ganged armature and contact set 52 (FIG. 2A) is provided with the channel select switch 52 for use in a Balance operation. In FIG. 2D are also shown a balance switch S4 and an enter switch 55, both of the single action type. The latter switch 55 is more fully described as an enter set point switch.

At the input end of the system (FIG. 2A), the operator is able to adjust, for each channel, each of a set of four potentiometers 60, 61, 62 and 63, these being the high limit, high alarm, low limit and low alarm potentiometers respectively. Each channel also provides a switch 67 (FIG. 2E) for selecting forward or reverse control, and in this conjunction it should be noted that the terms Forward-Positive and Forward Positive are the inverse of each other. At the output end of the system, the operator can also adjust individual potentiometers 65 for each channel, after engaging an automatic-manual selector switch 66 appropriately to provide manual control for selection of the setting of the associated control unit. Additionally, there is for each channel a switch designated as the cascade switch 68, used in the performance of a selectable data interchange function described in greater detail below.

The recirculating storage 30, together with the read amplifier and write amplifier circuits 31, 32 respectively are shown only in general form in FIG. 2E. The address ing circuits 70 for control 0f entry and extraction of data from the recirculating storage 30 are also shown only generally, inasmuch as these addressing circuits may be conventional. The set point and integral values for each channel are stored at separate locations in the storage, and a channel counter 72 controls sequencing of the multiplexers and other synchronously operated units by determining the channel at which the set point and integral values are reproduced and entered during operation. The channel counter 72 is used in conjunction with many other gating and selection functions as well. The channel counter 72 may be a conventional step counter having one extra position n in addition to the twenty positions chosen for the present example. It may comprise an interconnected chain of bistable elements or a binary counter together with an output matrix, but has not been shown in detail for simplicity. The 21st position, designated n, is a dummy or number position used for entry of a manually adjusted set point through a potentiometer 71 (FIG. 2A).

The system also employs two basic clock signals, a l mc. clock 73 (FIG. 2B) being utilized in sequencing through various states and in the generation of the serial pulse trains representative of digital counts, and a 5 c.p.s. clock 74 (FIG. 2C) being utilized to control scanning of the individual channels at five times per second. These rates may be adjusted as desired, although they are representative of suitable clocking rates for data transfer and loop scanning in a typical digital process control system.

The following detailed description of various operative sequences include the entry of the PV signal, the two term computation and the generation of the output control signal. While they may encompass all the modes 301- 312 illustrated in FIG. 3, they are not arranged in chronological order but with respect to separate functions. Concurrently there are described Various features by which great flexibility and operative convenience are imparted to the system without a commensurate increase in equipment or cost. It will be understood that the description is concerned primarily only with a single channel, and that similar operations take place for each channel, in sequence.

ENTRY OF DATA The following description is concerned primarily with the derivation and conversion of the signals utilized for the subsequent two term control computation. Although reference is made to various parts of FIG. 2, primary reference is to FIG. 2A, and to FIGS. 3A and 3B. Among the features included in this portion of the system are an arrangement by which the analog input signal is '7 checked for alarm violations, another feature by which the operator is prevented from utilizing a set point outside the preset limit values, and also a feature by which new set points may be simply but readily selected and then entered into the system.

The analog to digital converter 26 in FIG. 2A principally uses a ramp generator 76 that may be triggered to initiate a linearly descending wave form under control of a circuit here shown separately as a ramp run circuit 77. The c.p.s. clock signal initiates scanning of the succession of channels, or the channel counter 72 shifts from one channel to the next, starting a transitory startconvert mode (not shown in FIG. 3) that removes a reset bias from the ramp run circuit 77. This event initiates the convert mode illustrated in FIG. 3A. With the input multiplexer coupling an appropriate channel to the analog to digital converter 26, and the process variable being provided as an analog signal on the input line, the ramp generator 76 initiates the linearly decreasing ramp wave form. The ramp signal is coupled to activate one input of each of a succession of four detection circuits labeled successively the high detect circuit 80, the low detect circuit 81, the first detector 82 and the second detector 83. In the absence of limit or alarm conditions, the first and second detectors 82, 83 control the analog to digital conversion. In the start-convert mode, the ramp generator 76 continues to operate as it passes down through the level of the PV signal provided from the multiplexer 25. The first detector 82, however, fires whenever the ADC ramp is equal to the selected input signal amplitude, activating the gate 115 (FIG. 2B) and applying pulses from the l mc. clock 73 to the count input of the A register 28 (FIG. 2C). The counting operation and subsequent operations are described below with respect to the computation function, and it suices here to say that the counting sequence continues until the second detector 83 is actuated at a selected reference level, here designated El., In the present instance, a voltage level of one volt is selected for the minimum, or reference, and the ramp generator 76 is arranged in conventional fashion to provide a ramp signal in the range from approximately 6 volts downward. The set points are for convenience set in the range from 0 to 999 and are computed and displayed in this form.

Firing of the second detector 83 terminates the convert mode and initiates a subsequent mode which may be designated as ready 1 (FIG. 3B), in which the summing counters 28, 35, 36 are set to count in appropriate directions. A signiiicant number of features are provided in conjunction with this basic analog to digital conversion circuitry. First it may be noted that the PV signal may be less than one volt in amplitude, so that the second deltector 83 may lire before the first detector S2. If this occurs, during the convert mode under range gate 118 (FIG. 2B and FIG. 3A) is activated, actuating an under range latch 85 that reverses the sense of counting in the A register 28 (FIG. 2C) through a sequence of gates 170, 172 (also shown in FIG. 3C). Note that in the convert mode 301 (FIG. 3A), the 2 mode control latch also is on, to fully condition the gate 170. The A register 28 is normally set to count up when entering the PV digital value and this reversal of the sign enables an appropriate value to be entered.

A further important feature of this arrangement is the fact that it permits the alarm settings to be determined by the potentiometers 61, 63 for the particular channel. In the convert mode, a set of gates 84 (FIG. 2A) coupled to the channel counter 72 (FIG. 2E) complete circuits to the high alarm switches 86 and low alarm switches 87 (FIG. 2A) for the particular channel, so that these are coupled to the high and low detectors 80, 81 respectively. The ramp signal from the generator 76 is concurrently applied to the high and low detectors 80, 81. A time comparison is also made in a pair of associated gates 119, 120 (FIGS. 2B and 3A) as to the relative times in which the high, low and first detectors, -82 respectively, tire. If the rst detector 82 tires prior to firing of the high detect circuit 80, the gate 120 activates the appropriate channel of alarm indicators 89 through input control gates 100, 119, 120 (FIG. 2B) scanned by the channel counter 72 (FIG. 2E). lf the low detect circuit 81 fires prior to the iirst detector 82, the output of which is taken through an inverter circuit, a second AND gate 119 coupling into the alarm indicator gating circuits is activated for that particular channel, as shown in FIGS. 2B and 3A, It will be appreciated that these tests and indications are provided concurrently with basic analog to digital conversion, so that no extra time is required for the alarm check. Furthermore, only relatively simple alarm circuitry is associated with each individual channel, eliminating the need for a central storage facility as well as the need for separate comparison functions and equipment.

It will also be noted that high limit 90` and low limit 91 switches are provided for each channel, these being controlled by separate channel selection gates 93 activated during the compute error mode (which may also be referred to as error compute) and individually selected in accordance with the state of the channel counter 72. While the compute error mode will be described below in conjunction with the two term integration, that aspect concerned with the automatic utilization of high and low set point limits in the system exists during ready 1 and is directly pertinent to the input control function. To appreciate the operation of these units, further brief discussion of the functioning of the B register 35 (FIG. 2D) is in order. The process variable is entered into the A register 28 as previously described, with the set point being entered into the B register 35 from the storage 30 (FIG. 1). This is accomplished previous to the error compute mode, so that the two registers 28 and 35 may be counted down simultaneously with the number of pulses remaining in one after the other has reached zero representing the desired error value. Under certain conditions of operation, however, as in start-up or other transient states, the set point in the storage may not be useful as such. Also, because of operator error or other causes, an erroneous set point outside of limits predetermined for the system may be entered. The settings of the limit resistors 60, 62 are used to control the range of set points that may actually be utilized.

It should particularly be noted, however, that the low limit potentiometer 62 is not truly a low set point element. It is more appropriately referred to as a span limit potentiometer, because it does not constitute an absolute low limit but serves as a reference from which an acceptable range is defined. This span limit function permits simplification of the circuitry, and is described in detail hereafter.

In the error compute mode, the ramp generator 76 is again initiated after closure of the input switches 90, 91 controlled by the gates 93 in correspondence to the particular channel then in use. In the error compute mode, the A register 26 is counted down by the clock pulses from the source 73 as shown by gate 150 in FIG. 3B and FIG. 2B. Initiation of the ramp pulse from the generator 76 causes the high detector 80 to re first, coupling the l mc. clock to the A register. At the same time, 1 mc. clock signals are coupled to the count input of the B register 35, through a gate 149 (FIG. 2D) that is fully activated because of the presence of the B7-0 and the high detect signal. Thus the countdown of both registers 28, 35 takes place simultaneously, with the pulses generated during this interval representing the set point accumulation. In this mode, the first detector 82 is not utilized, but the outputs from the low detector 81 and the second detector S3 (FIG. 2A) alone determine the total number of serial set point pulses actually used. Normally, when the set point is in the desired span, the B register will count down to zero somewhere between the time of the iiring of the low detector 81 and the second detector 83. If this occurs, the low detector 81 fires iirst. Then when the Ba signal terminates, the Bee() signal input goes false, and the output taken from the inverter goes true,7 representing B=0. This term, plus the low detect signal activate an and gate whose output is inverted to disable the gate 150, terminating the application of pulses to the A register 28. Concurrently, the gate 149 is disabled because of the termination of the BeO signal. The count remaining in the A register 28 therefore represents the error quantity.

If, however, the B register 35 counts down to zero before the low detector 81 or after the second detector 83, it is outside the desired limits. Thus, the span in which the set point must fall (given a start point established by the high detector 80) is actually determined at a minimum value of pulses established by the low detector S1, and the maximum value of pulses is then established by the second detector 83. This span voltage therefore defines the true set point limits.

In the event that the B register 35 counts to zero prior to the ring of the low detector 81, counting pulses continue to be forced through the gate 150 for application to the A register 28 until the low detector 81 fires. In effect, the set point is established at its lowest limit because the error will be largest at this point in the span. When the second detector 83 fires, the gate 150 is disabled, regardless of whether or not the B register is at zero. This insures that the countdown of the A register 28 is terminated upon tiring of the second detector 83 in any event.

To summarize, therefore, the span range is determmed by the low detector 81, which detects the lower limit on the ramp, and also the lower limit on the set point, because if the chosen set point would give a greater error, the B register 35 counts down to zero before the detector lires, and the detector therefore decreases the error by this amount. On the other hand, if the stored set point is excessive, the second detector lires to generate the upper limit of the set point and to provide the minimum error signal. The `maximum acceptable value for the set point is set by the high limit potentiometers l60 rwhich in effect starts the count. The span of the set point limits, as well as the actual minimum and maximum set point values, is then determined by the setting of the low limit potentiometer l62. For this reason, the number of counts between the high limit and the low limit, as well as the range, are varied by adjusting only the low limit potentiometer.

Important advantages are derived from this arrangement, inasmuch as it enables realistic set points to be used and also enables the system to be operated under operator control during transient states. During start-up, for example, the set p oint may be set outside the limiting range, typically at a maximum value. In this instance, the set point that is actually used is determined by the setting of the high limit potentiometer which starts the set point count, because the count continues until the second detector 83 is fired. When the appropriate stable set point is reached as the process system moves toward a steady state condition, the value of the setting of the high limit potentiometer 60 can be read in the display, in a manner described below, and then entered as a new set point. Another advantage of this arrangement is that it provides an automatic fail-safe feature, in that the limits are continuously tested during normal operation. In the event that a stored set point is lost or some error occurs, the limiting values automatically control.

SET POINT ENTRY The manner in which the set point for an individual channel may be varied by an operator will be principally described with respect to FIG. 2, and principally involves the channel counter 72 (FIG. 2E) the channel select switch 52 and display function switch 50 (FIG. 2D) and the set point enter potentiometer 71 (FIG. 2A).

It was previously stated that the channel counter 72 contains an extra digital place, constituting a dummy position designated as the number or n position. When in this 21st position, the channel counter 72 generates ya number signal to condition a gate 112 (FIG. 2A and FIG. 3A) energizing a gate 96 that controls a 21st position switch 97 in the multiplexer 25, closing the switch to couple the set point enter potentiometer 71 to the irst detector 82. This enables a signal at a level determined by the setting of the potentiometer 71 to 4be entered into the analog to digital converter 26. Concurrently for this operation, the display function switch 50 (FIG. 2D) is set to the set point enter position, and the enter set point switch 55 is closed, actuating the enter latch 98 through a gate 203 (FIG. 2D and FIG. 3F). The system includes, as generally shown in FIG. 2C, a display register 99, including a resettable counter (not shown) for accumulating a series of pulses representative of a binary value, and appropriately converting to decimal values for convenience. In FIGS. 2B and 3A, it is seen that the gate 102 is activated during the number state because of the settings of the display function switch 50, and the channel select switch 52, with the display having been reset prior to this time. At the dummy or number position of the channel counter 72, therefore, the l rnc. clock pulses are applied to the gate 102 for a duration determined by the interval between the tiring of the first detector 82 and the second detector 83 in the analog to digital converter 26. The pulses are totalled in the display register 99, and the totals are displayed for the operator. This action occurs each time the number state is reached at the end of a scan of the various channels, or live times per second. From the standpoint of the operator, the displayed count changes concurrently with his adjustment of the entry potentiometer 71, so that he can directly observed in digital form the setting he is making for a particular selected channel.

Once the chosen setting has been reached, the set point is required to be entered into the appropriate channel and into the recirc-ulating storage at the appropriate point. For this purpose, the enter latch 98 is now actuated by closing of the enter set point switch 55, as previously described, with the channel select switch 52 being at the desired channel position. This is accomplished during the next scan of the given position, by entry of the chosen set point from the potentiometer 71 (FIG. 2A) into the B register 35 through the gate 104 (FIG. 2B and FIG. 3A). The gate 104 is opened to pass 1 mc. clock pulses for an interval initiated by the firing of the first detector 82 in the ADC 26, the interval being terminated by the tiring of the second detector 83. The applied pulse series is accumulated in the B register 35, and thereafter transferred into the recirculating storage 30 system, during succeeding modes that are discussed in detail below.

It will be noted that apart from the set point entry potentiometer 71 and a relatively few gates and switches, this system utilizes existing units of the process control system in an inter-related fashion. The problem of entry of a selected digital value is thereby solved at minimum expense, but with full operator convenience. These features are made posible through the use of the dummy position in the machine cycle, and the relationship of the analog, manually controllable, input to the analog to digital converter and the display and B registers. A direct technique for the entry of a digital value is provided that is far less expensive than other available expedients conventionally used. The potentiometer adjustment and comparison to a concurrent digital display are particularly easy for an operator to utilize and understand. Furthermore, separate mechanisms are not required for each individual line, and no special addressing or other circuits are required.

It is convenient to note here that normal operation of the system maintains the output signal for the previous (n-l) channel through the convert to transfer integral to C modes (FIG. 2E), and then switches to the newly generated signal in the advance channel mode. When l ll using balance" or enter for a given channel, howvever, the output inhibit latch 398 (FIG. 2D) is set, `blocking the sample and hold output signal. This latch is not reset on the first advance channel signal, but on the one thereafter, because the balance or enter switch 54 or 55 for the channel turns its associated latch on at the first advance channel signal. Thus output signals are not provided on the selected channel as they normally would be.

TWO TERM COMPUTATION The function of modifying the error signal for a particular channel in accordance with both integral and proportional terms, selectively adjusted as to gain, has been `briefly referred to above. This portion of the system relates primarily to FIGS. 2C, 2D and 2E, and virtually all of FIG. 3. The following description pertains not only to the manner in which the three summing counters 28, 35 and 36 are utilized, but particularly to the manner in which the gain adjustment circuits (designated 33 and 34 in FIG. l) operate. Note that separate integral gain circuits 34a-t inclusive are used for the different channels. Ertry of representations into the display, and the manner of entry into and reading from the recirculating storage, will be referred to generally here, but are set out in more detail below.

Both the A register 28 (FIG. 2C) and the B register 35 (FIG. 2D) include ten binary bits for counting from 0 to 1023. The B register 35 is limited in this respect, and does not count over-range or under-range. The A register 28, however, includes additional bits for counting overrange and under-range. Both the registers operate as reversible summing counters, and have up and down inputs at which the directions of the counts may be reversed. Each register also includes an input to which the pulses to be counted are applied, and a reset input, as well as conventional means (described as part of the register for convenience only) for identifying predetermined counting states. In the R register 28 the predetermined states are A= and its inverse, and A=l023 and its inverse; in the B register 35 the predetermined states are B=0 and its inverse, and B=l023 and its inverse. The C register 36 corresponds to the A register 28, in that it 'has both under-range and over-range conditions, and may be counted negative prior to being counted in the opposite direction during the two term control computation.

On entering the convert mode, a gate 208 (FIG. 2D and FIG. 3F) is actuated as a function reset signal and applied to the reset input of the A register 28, with the B register 35 being reset through a gate 220 (FIG. 2D and FIG. 3G) thereafter. Then, during the convert mode as previously described, the value of the process variable is entered into and held in the A register 28. During convert also, the addressing circuits 70 for the recirculating storage (FIG. 2E) select the set point to be read into the B register through a gate 117 (FIG. 2E and FIG. 3A). This count comprises a serial binary number read into the appropriate parallel digital positions of the B register 35 through a group of gates 320 (FIG. 2D). Note that these gates 320` are also associated with a separate data register, 319 and may, alternatively be used for the external entry of a chosen set point into the B register 35. Separate gates 321 are used to read out the B register 35 contents. The C register 36 is concurrently reset through a gate 200 (FIG. 2E and FIG. 3F).

The sign of the quantity in the A register 28` is controlled by an over-range latch 322, and under-range latch 85 and an ADC sign latch 324 (FIG. 2B). The overrange latch is set by a gate 325 in the event that the count of A-1023 is reached prior to firing of the second detector, and latching of this circuit 322 conditions a gate 147 during the compute error mode to set ADC sign latch 324 positive. This in turn conditions a gate 171 that controls the gate 172 (FIGS. 2C and 3C) that set the A register 28 to count down. Various functions, insuring I2 that proper arithmetic signs are used, are employed and these are described in more detail below. The generation of the error signal then takes place during the compute error mode.

Appropriate provision is further made for the nature of the control being exercised, Whether forward or reverse, and for the situation in which the process variable is under range. In the event that either the forward or positive condition obtains, the sign of the ADC sign latch 3214 is reversed, causing the A register 28 to count in the opposite direction so as to effectively reverse the sense of subtraction of the process variable, with respect to the set point. Similarly, if the under-range latch is set through the gate 118 (FIG. 2B) lbecause the second detector 83 is fired before the first detector 82 in the ADC 26, the A register is set to count up during the compute mode beause of a negative quantity is in effect represented. The count down or count up relationship at the up and down input terminals to the A register 28 is established by a set of gates 130, 131 and 170 responsive to the `under-range latch (FIG. 2C, FIG. 3A and FIG. 3C).

As a result of these relationships, the system in the compute error mode drives the counts in the A register 28 and B register 35 simultaneously to a state in which the A register contains the error quantity. This error quantity is to be passed through the gain adjustment circuits 33, 34 that introduce the proportionality terms KI and Kp, with the integral term being entered into the B register 35 (FIG. 2D) and the proportional term being entered into the C register 36 (FIG. 2E). At this point the A register 28 is set to count down or up, according to the sign of the error, and the system enters an address delay line mode 304 (FIG. 3C), in which the gate 117 (FIG. 2E) reads the integral from the recirculating storage 30 into the appropriate channel of the B register 35, in the manner previously described with respect to the set point. During this mode and the subsequent ready 2 mode (FIG. 3C) the various sign adjustments are made (FIG. 3C).

The system therefore is enabled to enter a two term compute mode 306, shown in FIG. 3D and principally described with respect to FIG. 2C as well. In FIG. 2C, the proportional gain circuits 33 and the integral gain circuits 34 are seen to receive the clock signal also applied to the count input of the A register 28 from a gate 181 that remains activated until the A register 28 is brought to zero. The proportional gain circuits 33 comprise a pair of digital count division systems, one working from a l mc. clock 340, here shown separately from the clock 73 for convenience only, and the other working from a 0.7 mc. clock 342. The l mc. clock 340 is gated through a succession of binary count dividers 344, 345, 346 and 347, each providing a further half division of the frequency of the l mc. signal, down to a 1/16 division. The 0.7 mc. clock 342 is passed to a succession of three binary dividers 349, 350, 351, providing a succession of different values of frequency. The amplitude of the error signal in the A register 28 is not only represented by the number of pulses contained therein, but by the duration of the count interval at 1 mc. that is used in returning the A counter 28 to zero. Thus a group of gates 370 at the output terminals of the frequency dividers are controlled in part by the signal derived from an input gate 181. This signal permits a selected one of the gates 370, as controlled by the channel counter 72, a 9 position switch 371 for each channel, to open for a time specifically related to the quantity in the A register 28. A related number of pulses is then provided on the output line through separate gates 18M-t for the channels (FIGS. 2C and 3D) to the C register 36, for summation therein. The selection of a particular value of frequency or count division by actuation of one of the gates 370 may also be controlled by the channel counter 72, through a preset gate network if desired. Alternatively, if desired, a separate proportional gain circuit 33 and integral gain circuit 34 may be utilized for each channel.

When the A register 2.8` is counted down at the l mc. rate, the proportional gain circuits 33 operate as a variable count divider to provide a fractional gain constant. Through use of a cross-coupling switch 37l2a-t, however, the l mc. clock pulse series may be applied tothe C register 36, while the lower pulse rate is applied to the A register 28, to provide a gain constant at a multiplication factor. Thus the number of digitally related gain constants for the proportional gain term is doubled, and the proportional term may be made predominant for chosen control loops.

In the integral gain circuits 34, the number of pulses stored in the A register 28 is utilized in generating the new integral term component derived from the error signal. The integral gain circuits 34a-t, one for each channel, include two different frequency division systems, one of which represents the variable frequency switch S2 designated in FIG. l, and the other of which represents a variable frequency division system. The variable switch is designated as a multi-rate sampler 380, and may be a preset counter operable in response to the 5 c.p.s. clock 74, and effective to open an input gate 182 only once for each predetermined number of times the channel is scanned in succession. A conventional counting and gating system may also be utilized for this purpose, and is of course adjustable to permit selection of this portion of the gain constant. The remaining portion of the integral gain term is determined by a selected count division network 383, 384, 385, here shown as consisting of three stages for simplicity, although any additional number may be used. The integral gain adjustment, therefore, is widely variable over a great range, depending upon the integral gain constant to be used. If a very small fractional gain quantity is to be used as the multiplication term for the error, the multi-rate sampler 380 is closed only once every high number of scans of that channel, opening the gate to pass the pulses representing the error term only during that selected cycle. The number of pulses are further reduced in lnumber in the selectable frequency divider 383, 384, 385, so that the output pulses passed to the B register through the gate 183 contribute only the new component of the total updated integral term to the count of the integral already contained in the B register 35. A rotary switch 387 permits selection of the appropriate division ratio for the channel.

The two term compute mode is completed in either of two ways. When the A register 28 is, in the typical situation, counted down to zero, the count terminates. Both gates 183a-t and 184a-t (FIGS. 2C and 3D) are thereafter deactivated, and the gate controlling entry into the Write storage mode 307 (FIG. 3E) is activated. Alternatively, if the C register 36 is saturated by reaching zero or a full count, dependent upon whether forward or reverse control is used, further pulses are blocked off from the C register at the gate 184a-t, inasmuch as this indicates that the associated valve will be fully opened or closed. Again the system advances to the write storage mode.

This arrangement has the advantage of providing a high division factor for the integral term, without requiring a long string of dividers. Furthermore, both the integral and proportional gain circuits are alike in form, and operate in response to the quantity contained in the A register, so that no further conversion is needed. This arrangement also enables the proportional quantity to be given any precisely selected increment of gain, while the integral gain can be chosen very small.

Further significant advantages are derived from the essentially digital nature of the integral gain circuits and the digital storage of the integral. Where extremely low gain terms are required, analog systems have been adopted with the consequent disadvantages of drift.

Because the integral is accumulated and stored in digital fashion, an essentially infinite time constant can be utilized, and the integral itself is effectively free from change or error. Thus the same precision need not be applied to each integral increment, because over a period of time such errors will average to zero. In a practical example of a system in accordance with the invention, the integral gain constant may be so low that an increment is added to the integral term only once in a number of hours or even days. Further, the selectable frequency divider 383, 384, 385, provides storage of the accumulated count, so that during the count division none of the pulses passed by the multi-rate sampler 380 are lost despite the lengthy durations of time between passage of samples under the control of the multi-rate sampler 380. With this arrangement, the multi-rate sampler 380 may be a semi-digital or analog device, such, as a staircase generator, if desired.

In the two term compute mode 306 (FIG. 3D) the B register 35 and `C register 36 are set to count in appropriate directions by a group of gates 174, 175, 174A and 175A (FIG. 2D). Dependent upon the source of pulses selected in the proportional gain channel, the proportional component is passed through the gate 184 (FIG. 2C and FIG. 3D) to be counted in the C register 36, at the same time the new integral increment is being added in an appropriate sense to the integral term stored in the B register 35.

In the next succeeding mode directly concerned with generation of the control signal, the transfer integral to C mode 308 (FIG. 3E), the C register 36y is set to count up, the B register 35 previously having been set to count back down to zero. The l mc. clock pulses are applied to gate 196 (FIG. 2D and FIG. 3E) that continues to pass the clock pulses until the B register 35 returns to zero or the C register 36 is full (reaches 1023). In either event, the count remaining in the C register 36 constitutes the sum of the integral and proportional terms, and represents the control signal in digital form. The digital value is converted to an analog equivalent in the digital to analog converter 40, and is thereafter coupled to the appropriate output terminal in a sequence beginning with the advance channel-set DAC mode 309 (FIG. 3F).

In the output circuits, an operational amplifier 390 coupled to the digital to analog converter 40 (FIG. 2E) applies signals through switches 392 in the output multiplexer 41, the signal level being retained in a storage capacitor 393 for a length of time Sufficient to effect proper adjustment of the output controller. During the successive modes from convert to transfer integral to C the count held in the channel counter 72 represents the selected channel, terminal n, but the output multiplexer 41 is arranged to hold the position for the previous (rz-1) channel, by an arrangement of output switching control gates 395. After these modes have been sequenced, an appropriate gate in the output switching control gates 395 is activated, to close the appropriate switch 392 in the multiplexer 41 and to set the nal state of the digital to analog converter 40 into the appropriate output channel to the process system. A capacitor 393 in the holding amplifier circuits 43 is charged to the final level, and maintains the level as a control signal for the output amplifier 396 for the channel, so that the associated controller is responsively adjusted.

ADDITIONAL MODES AND SYSTEM FEATURES Provision of an appropriate control signal for the particular channel terminates the operation on the channel, and permits the system to proceed to the next channel. The changeover must, however, be accomplished 

